1. Field of The Invention
The present invention is generally in the field of electrical circuits. More specifically, the present invention is in the field of memory sensing and latching circuits.
2. Background Art
A continuing problem facing manufacturers of memory arrays, such as random access memory (RAM) arrays, static random access memory (SRAM) arrays, and content-addressable memory (CAM) arrays, is reducing “memory cycle time,” which can be defined as the minimum time interval between starts of successive read/write cycles. In order to minimize memory cycle time, it is important to utilize a fast sense amplifier, such as a “drain-fed” sense amplifier, to sense, amplify, and output data on bit lines in a memory array. The expression “drain-fed” refers to the coupling of the bit lines to the drains of the transistors that typically form a pair of cross-coupled inverters in the drain fed sense amplifier.
In a sense amplifier, such as a drain-fed sense amplifier, the output of the sense amplifier is driven by the input of the sense amplifier, which is coupled to bit lines of the memory array. However, the bit lines that are coupled to the sense amplifier cannot be precharged until the output of the sense amplifier has been stored in a latching circuit. A conventional latching circuit can include a pair of cross-coupled inverters, which are coupled to the output of the sense amplifier. As a result, the output of the sense amplifier has to be held in its selected state for a long duration to allow the conventional latching circuit to store the output of the sense amplifier, which can undesirably increase memory cycle time. Also, a large-size output buffer is typically required to drive a conventional latching circuit, which can undesirably increases the area consumed by the sense amplifier and its output buffer, and also imposes additional capacitive loading on the bit lines.